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參數(shù)資料
| 型號： | MPE603ERX100LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 250K |
| 代理商： | MPE603ERX100LX |
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PID6-603e Hardware Specifications, Rev 2
11
Figure 4 provides the output timing diagram for the 603e.
Figure 4. Output Timing Diagram
1.4.3 JTAG AC Timing Specications
Table 9 provides the JTAG AC timing specications as dened in Figure 5 through Figure 8.
Table 9. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions. See Table 2. CL = 50 pF
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
16
MHz
1
TCK cycle time
62.5
—
ns
2
TCK clock pulse width measured at 1.4 V
25
—
ns
3
TCK rise and fall times
0
3
ns
4
TRST setup time to TCK rising edge
13
—
ns
1
5
TRST assert time
40
—
ns
6
Boundary-scan input data setup time
6
—
ns
2
7
Boundary-scan input data hold time
27
—
ns
2
8
TCK to output data valid
4
25
ns
3
9
TCK to output high impedance
3
24
ns
3
SYSCLK
12
14
13
15
16
TS
ARTRY
ABB, DBB
VM
VM = Midpoint Voltage (1.4 V)
15
VM
13
20
18
17
21
19
ALL OUTPUTS
(Except TS, ABB,
DBB, ARTRY)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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