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參數資料
| 型號： | MPE603ERX100LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數： | 2/32頁 |
| 文件大?。?/td> | 250K |
| 代理商： | MPE603ERX100LX |
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10
PID6-603e Hardware Specifications, Rev 2
1.4.2.3 Output AC Specications
Table 8 provides the output AC timing specications for the 603e as dened in Figure 4.
Table 8. Output AC Timing Specifications1
At recommended operating conditions. See Table 2., CL = 50 pF
2
Num
Characteristic
100 MHz
133.33 MHz
Unit
Notes
Min
Max
Min
Max
12
SYSCLK to output driven (output enable time)
1.0
—
1.0
—
ns
13a
SYSCLK to output valid (5.5 V to 0.8 V—TS, ABB,
ARTRY, DBB)
—
11.0
—
11.0
ns
4
13b
SYSCLK to output valid (TS, ABB, ARTRY, DBB)
—
10.0
—
10.0
ns
6
14a
SYSCLK to output valid (5.5 V to 0.8 V—all except TS,
ABB, ARTRY, DBB)
—
13.0
—
13.0
ns
4
14b
SYSCLK to output valid (all except TS, ABB, ARTRY,
DBB)
—
11.0
—
11.0
ns
6
15
SYSCLK to output invalid (output hold)
1.5
—
1.5
—
ns
3
16
SYSCLK to output high impedance
(all except ARTRY, ABB, DBB)
—
9.5
—
9.5
ns
17
SYSCLK to ABB, DBB, high impedance after precharge
—
1.2
—
1.2
t
sysclk
5,7
18
SYSCLK to ARTRY high impedance before precharge
—
9.0
—
9.0
ns
19
SYSCLK to ARTRY precharge enable
0.2 *
t
sysclk
+ 1.0
—
0.2 *
t
sysclk
+ 1.0
—
ns
3,5,8
20
Maximum delay to ARTRY precharge
—
1.2
—
1.2
t
sysclk
5,8
21
SYSCLK to ARTRY high impedance after precharge
—
2.25
—
2.25
t
sysclk
5,8
Notes:
1. All output specications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8
V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see
Figure 4).
2. All maximum timing specications assume CL = 50 pF.
3. This minimum parameter assumes CL = 0 pF.
4. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external
voltage from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5 V CMOS levels instead of 3.3 V CMOS levels).
5. t
sysclk
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the
table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of
the parameter in question.
6. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V.
7. Nominal precharge width for ABB and DBB is 0.5 tsysclk.
8. Nominal precharge width for ARTRY is 1.0 tsysclk.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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