參數(shù)資料
型號(hào)： MPE603ERX100LX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255
封裝： 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255
文件頁(yè)數(shù)： 23/32頁(yè)
文件大?。?/td> 250K
代理商： MPE603ERX100LX
PID6-603e Hardware Specifications, Rev 2
3
1.2 Features
This section summarizes features of the 603e’s implementation of the PowerPC architecture. Major features
of the 603e are as follows:
High-performance, superscalar microprocessor
— As many as three instructions issued and retired per clock
— As many as ve instructions in execution per clock
— Single-cycle execution for most instructions
— Pipelined FPU for all single-precision and most double-precision operations
Five independent execution units and two register les
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR), special-purpose register (SPR) instructions, and
integer add/compare instructions
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for single- or double-precision operands
High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 16-Kbyte data cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— 16-Kbyte instruction cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— BPU that performs CR lookahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast-trap mechanism
— 52-bit virtual address; 32-bit physical address
Facilities for enhanced system performance
— A 32- or 64-bit split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)PDF資料
PDF描述
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