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PD705101
31
15. INSTRUCTIONS
15.1 Instruction Format
The V831 uses two instruction formats: 16-bit and 32-bit. The 16-bit instructions include binary operation, control,
and conditional branch instructions, while the 32-bit instructions include load/store and I/O operation instructions,
instructions for handling 16 bits of immediate data, and jump-and-link instructions.
Some instructions contain unused fields, which must be fixed to 0, which are provided for future use. When an
instruction is actually loaded into memory, its configuration is as follows:
Low-order part of each instruction format (including bit 0)
→
Low-order address
High-order part of each instruction format (including bit 15 or 31)
→
High-order address
(1) reg-reg instruction format [FORMAT I]
This instruction format has a six-bit operation code field and two general-purpose register designation fields for
operand specification, giving a total length of 16 bits.
reg 1
0
4
5
9
10
15
opcode
reg 2
(2) imm-reg instruction format [FORMAT II]
This instruction format has a six-bit operation code field, a five-bit immediate data field, and a general-purpose
register designation field, giving a total length of 16 bits.
15
10 9
5 4
0
imm 5
reg 2
opcode
(3) Conditional branch instruction format [FORMAT III]
This instruction format has a three-bit operation code field, a four-bit condition code field, a nine-bit branch
displacement field (bit 0 is handled as 0 and need not be specified), and a one-bit sub-operation code, giving a
total length of 16 bits.
15
13 12
9 8
1 0
s = 0 : Bcond
s = 1 : ABcond
s : sub-opcode
opcode
cond
disp 9
s