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參數(shù)資料
| 型號： | MPC9855 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Clock Generator for PowerQUICC and PowerPC Microprocessors |
| 中文描述： | 微處理器時鐘發(fā)生器為PowerQUICC和PowerPC |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 267K |
| 代理商： | MPC9855 |
Timing Solutions
Freescale Semiconductor
5
MPC9855
OPERATION INFORMATION
Output Frequency Configuration
The MPC9855 was designed to provide the commonly
used frequencies in PowerQUICC, PowerPC and other mi-
croprocessor systems.
Table 3
lists the configuration values
that will generate those common frequencies. The MPC9855
can generate numerous other frequencies that may be useful
in specific applications. The output frequency (f
out
) may be
calculated by the following equation.
f
out
= 2000 / N
where f
out
is in MHz and N = 2 * CLK_x[0:5]
This calculation is valid for all values of N from 8 to 126.
Note that N = 15 is a modified case of the configuration inputs
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
00111 or 7.
Crystal Input Operation
The MPC9855 features a fully integrated Pierce oscillator
to minimize system implementation costs. Other than the
addition of a crystal no external components are required
The crystal selection should be 25 MHz, parallel resonant
type with a load specification of C
L
= 10 pF.
The crystal should be located as close to the MPC92469
XTAL_IN and XTAL_OUT pins as possible to avoid any board
level parasitic.
Power-Up and MR Operation
Figure 2
defines the release time and the minimum pulse
length for
MR
pin. The
MR
release time is based upon the
power supply being stable and within V
DD
specifications. See
Table 10
for actual parameter values. The MPC9855 may be
configured after release of reset and the outputs will be stable
for use after lock indication is obtained.
Figure 2. MR Operation
Power Supply Bypassing
The MPC9855 is a mixed analog/digital product. The
architecture of the XC9855 supports low noise signal
operation at high frequencies. In order to maintain its superior
signal quality, all V
DD
pins should be bypassed by
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
Figure 3. V
CC
Power Supply Bypass
Power Consumption
The total power consumption of the MPC9855 may be
calculated by the following formula:
P = V
DD
* (I
DD
+ I
DDA
+ I
DDOC
) +
(CPD * frequency * * 4 * V
DDOA
**2) +
(CPD * frequency * 4 * V
DDOB
**2)
where frequency is the programmed output frequency for
bank A and bank B.
MR
V
DD
t
reset_rel
t
reset_pulse
V
DD
MPC9855
0.1
μ
F
22
μ
F
0.1
μ
F
15
V
DD
V
DDA
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參數(shù)描述 |
|---|---|
| MPC9855VM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9855VMR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9865VM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9865VMR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9893 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch |
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