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參數(shù)資料
| 型號(hào)： | MPC92474FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大小： | 172K |
| 代理商： | MPC92474FA |
Advanced Clock Drivers Devices
6
Freescale Semiconductor
MPC92474
PREL
IM
IN
AR
Y
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)
(1)
1. AC characteristics apply for parallel output termination of 50
to V
TT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fXTAL
Crystal Interface Frequency Range
12
40
MHz
fVCO
VCO Frequency Range(2)
2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL ÷ P * M.
560
700
MHz
fMAX
Output Frequency
N = 000 (
÷1)
N = 001 (
÷2)
N = 010 (
÷3)
N = 011 (
÷4)
N = 100 (
÷5)
N = 101 (
÷6)
N = 110 (
÷8)
N = 111 (
÷16)
560
280
186
140
112
93
70
35
700
350
233
175
140
116
87
43
MHz
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.05
0.3
ns
20% to 80%
fS_CLOCK
Serial Interface Programming Clock Frequency(3)
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See APPLICATIONS INFORMATION for more details.
010
MHz
tP,MIN
Minimum Pulse Width
(S_LOAD, P_LOAD)50
ns
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
ns
tS
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
ns
tJIT(CC)
Cycle-to-Cycle Jitter
TBD
ps
tJIT(PER)
Period Jitter
TBD
ps
t
Phase Noise
TBD
dBc/Hz
tLOCK
Maximum PLL Lock Time
10
ms
SSMfmod
Spread Spectrum Modulation Frequency
32
KHz
SSMdev
Spread Spectrum Modulation Deviation
SS[3:0] = 1010
SS[3:0] = 1100
SS[3:0] = 0010
SS[3:0] = 0100
-0.5
-1.0
+-0.25
+-0.5
%
fout = 200 MHz
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