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參數(shù)資料
| 型號： | MPC92474FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 172K |
| 代理商： | MPC92474FA |
Advanced Clock Drivers Devices
Freescale Semiconductor
3
MPC92474
PREL
IM
IN
AR
Y
Figure 2. MPC92474 48-Lead Package Pinout
(Top View)
Table 1. Pin Configurations
Pin
I/O
Default(1)
Type
Function
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
Analog
Crystal oscillators interface. See applications section for recommended crystal
specifications.
CLK,
CLK
Input
0
M
LVPECL
LVPECL clock input.
TEST_CLK
Input
0
LVCMOS
LVCMOS clock input.
FOUTA0, FOUTA0
FOUTB0, FOUTB0
Output
LVPECL
Differential clock outputs.
SEL0
SEL1
Input
0
LVCMOS
Reference input source select.
REF_CLK
Output
Reference clock output.
TEST
Output
LVCMOS
Test and device diagnosis output.
S_LOAD
Input
0
LVCMOS
Serial configuration control input.
This input controls the loading of the configuration latches with the contents of the
shift register. The latches will be transparent when this signal is high, thus the data
must be stable on the high-to-low transition.
P_LOAD
Input
0
LVCMOS
Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive.
1. A 0 represents an internal pulldown. A 1 represents an internal pullup. A M represents pulldown and pullup Vcc/2 biasing.
It is recommended to use an external
RC filter for the analog VCC_PLL supply
pin. Please see the application section
for details.
36 35 34
33 32
31
30
29
28
27 26
25
24
23
22
21
20
19
18
17
16
15
14
13
1 2
3
4
5
6
7
8
9
10
11
12
37
38
39
40
41
42
43
44
45
46
47
48
MPC92474
GND
P_DIV
VCCO_REF
REF_CLK
VCCOB
FOUTB0
VCCOA
FOUTA0
VCC
TEST
CLK
P_LOAD
VCO_SEL
M0
M1
M2
M3
M4
M5
M6
M7
XT
A
L_
O
U
T
1
XT
A
L_
IN1
XT
A
L_
O
U
T
0
XT
A
L_
IN0
TE
S
T
_C
LK
SE
L1
SE
L0
VC
C
_P
LL
S
_LO
AD
S_
D
A
TA
S_
C
LO
C
K
MR
M8
NB0
NB
1
NB2
OE
_R
E
F
OE
_A
OE
_B
VC
C
NA
0
NA
1
NA2
GN
D
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