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參數(shù)資料
| 型號： | MPC92474FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 172K |
| 代理商： | MPC92474FA |
Advanced Clock Drivers Devices
Freescale Semiconductor
9
MPC92474
PREL
IM
IN
AR
Y
Spread Spectrum Modulation
The MPC92474 offers the option of a spread spectrum
modulated output clock. The spread spectrum is controlled
via 4 bits in the serial bit stream. These three bits configure
the SSM to be enabled and the amount of spread modulation
to be selected. See Table 9 for the definition of the four bits.
The four additional bits are added at the beginning of the
serial data stream and are labeled SS3, SS2, SS1 and SS0.
The initial state of SS3, SS2, SS1 and SS0 is 0, 0, 0, 0 which
places the MPC92474 in the mode of spread spectrum off.
Additionally a parallel load will result in spread spectrum
modulation being off. The MPC92469 offers down-spread or
center spread using triangle-wave modulation.
Power Supply Filtering
The MPC92474 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCC_PLL pin impacts the device
characteristics. The MPC92474 provides separate power
supplies for the digital circuitry (VCC) and the internal PLL
(VCC_PLL) of the device. The purpose of this design technique
is to try and isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked
loop. In a controlled environment such as an evaluation
board, this level of isolation is sufficient. However, in a digital
system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may
be required. The simplest form of isolation is a power supply
filter on the VCC_PLL pin for the MPC92474. Figure 4
illustrates a typical power supply filter scheme. The
MPC92474 is most susceptible to noise with spectral content
in the 1 kHz to 1 MHz range. Therefore, the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop that
will be seen between the VCC supply and the MPC92474 pin
of the MPC92474. From the data sheet, the VCC_PLL current
(the current sourced through the VCC_PLL pin) is maximum
20 mA, assuming that a minimum of 2.835 V must be
maintained on the VCC_PLL pin. The resistor shown in
Figure 4 must have a resistance of 10-15
to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20 kHz. As the noise
frequency crosses the series resonant point of an individual
capacitor its overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL. Generally, the resistor/capacitor filter
will be cheaper, easier to implement and provide an adequate
level of supply filtering. A higher level of attenuation can be
achieved by replacing the resistor with an appropriate valued
inductor. A 1000
H choke will show a significant impedance
at 10 kHz frequencies and above. Because of the current
draw and the voltage that must be maintained on the VCC_PLL
pin, a low DC resistance inductor is required (less than 15
).
Figure 4. VCC_PLL Power Supply Filter
Table 9. SSM Operation
SS Bit Pattern
Operation
SS3
SS2
SS1
SS0
Mode
%
00
0
off
0
1
center
TBD
0
1
0
center
+-0.25%
0
1
center
TBD
0
1
0
center
+-0.5%
0
1
0
1
center
TBD
0
1
0
center
+-1.0%
0
1
center
TBD
10
0
off
0
1
0
1
down
TBD
1
0
1
0
down
-0.5%
1
0
1
down
TBD
1
0
down
-1.0%
1
0
1
down
TBD
11
1
0
cown
-2.0%
1
down
TBD
VCC_PLL
VCC
MPC92474
C1, C2 = 0.01...0.1 F
VCC
CF = 22 F
RF = 10-15
C2
C1
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