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參數(shù)資料
| 型號(hào)： | MPC92474FA |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 172K |
| 代理商： | MPC92474FA |
Advanced Clock Drivers Devices
Freescale Semiconductor
7
MPC92474
PREL
IM
IN
AR
Y
PROGRAMMING INTERFACE
Programming the MPC92474
Programming the MPC92474 amounts to properly
configuring the internal PLL dividers to produce the desired
synthesized frequency at each of the two outputs. The output
frequency can be represented by this formula:
FOUTA = (fXTAL ÷ P) x (M) ÷ (NA)
(1)
FOUTB = (fXTAL ÷ P) x (M) ÷ (NB)
(2)
where fXTAL is the crystal frequency, P is the prescale divider
value, M is the PLL feedback-divider and NA and NB are the
PLL post-divider for the outputs A or B. The input frequency,
the P divider and the selection of the feedback divider M is
limited by the VCO-frequency range. fXTAL, P and M must be
configured to match the specified VCO frequency range of
560 to 700 MHz in order to achieve stable PLL operation:
MMIN = fVCO,MIN ÷ fXTAL ÷ P and
(2)
MMAX = fVCO,MAX ÷ fXTAL ÷ P(3)
For instance, the use of a 16 MHz input frequency requires
the configuration of the PLL feedback divider between
M = 140 and M = 175. Table 7 shows the output frequencies
for the allowable M divider values for P = 4 and P = 8.
APPLICATIONS INFORMATION
Using the Parallel and Serial Interface
The M, NA and NB counters can be loaded either through
a parallel or serial interface. The parallel interface is
controlled via the P_LOAD signal such that a LOW-to-HIGH
transition will latch the information present on the M[8:0],
NA[1:0] and NB[1:0] inputs into the M and N counters. When
the P_LOAD signal is LOW the input latches will be
transparent and any changes on the M[8:0], NA[1:0] and
NB[1:0] inputs will affect the FOUT output pairs. To use the
serial port the S_CLOCK signal samples the information on
the S_DATA line and loads it into a 21 bit shift register. Note
that the P_LOAD signal must be HIGH for the serial load
operation to function. The SS register is loaded with the first
four bits,the test register with the next 2 bits, the NB register
with the next three bits, the NA register with the next three
and the M register with the final eight bits of the data stream
on the S_DATA input. For each register the most significant
bit is loaded first (SS3, T1, NB2, NA2 and M8). A pulse on the
Table 7. MPC92474 Frequency Operating Range
P
M
M[8:0]
Output frequency for fXTAL = 16 MHz and for N =
12
34
568
16
4
140
010001100
560
280
186.66
140
112
93.33
70
35
4
145
010010001
580
290
193.33
145
116
96.66
72.5
36.25
4
150
010010110
600
300
200
150
120
100
75
37.5
4
155
010011011
620
310
206.67
155
124
103.33
77.5
38.75
4
160
010100000
640
320
213
160
128
106.66
80
40
4
165
010100101
660
330
220
165
132
110
82.5
41.25
4
170
010101010
680
340
226
170
136
113.33
85
42.5
4
175
010101111
700
350
233.33
175
140
116.66
87.5
43.75
8
280
100011000
560
280
186.66
140
112
93.33
70
35
8
285
100011101
570
285
190
142.5
114
95
71.25
35.625
8
290
100100010
580
290
193.33
145
116
96.66
72.5
36.25
8
295
100100111
590
295
196.6667
147.5
118
98.33
73.75
36.875
8
300
100101100
600
300
200
150
120
100
75
37.5
8
305
100110001
610
305
203.33
152.5
122
101.6667
76.25
38.125
8
310
100110110
620
310
206.6667
155
124
103.33
77.5
38.75
8
315
100111011
630
315
210
157
126
105
78.75
39.375
8
320
101000000
640
320
213.33
160
128
106.66
80
40
8
325
101000101
650
325
216.6667
162.5
130
108.33
81.25
40.625
8
330
101001010
660
330
220
165
132
110
82.5
41.25
8
335
101001111
670
335
223.33
167.5
134
111.6667
83.75
41.875
8
340
101010100
680
340
226.6667
170
136
113.33
85
42.5
8
345
101011001
690
345
230
172.5
138
115
86.25
43.125
8
350
101011110
700
350
233.33
175
140
116.6667
87.5
43.75
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