參數資料
型號: MPC8321EVRADDC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA516
封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, PBGA-516
文件頁數: 80/80頁
文件大小: 1122K
代理商: MPC8321EVRADDC
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor
9
Power Characteristics
3
Power Characteristics
The estimated typical power dissipation for this family of MPC8323E devices is shown in Table 5.
Table 6 shows the estimated typical I/O power dissipation for the device.
Table 5. MPC8323E Power Dissipation
CSB
Frequency (MHz)
QUICC Engine
Frequency (MHz)
Core
Frequency (MHz)
Typical
Maximum
Unit
Notes
133
200
266
0.74
1.48
W
1, 2, 3
133
200
333
0.78
1.62
W
1, 2, 3
Notes:
1. The values do not include I/O supply power (OVDD and GVDD) or AVDD. For I/O power values, see Table 6.
2. Typical power is based on a nominal voltage of VDD = 1.0 V, ambient temperature, and the core running a Dhrystone
benchmark application. The measurements were taken on the MPC8323MDS evaluation board using WC process silicon.
3. Maximum power is based on a voltage of VDD = 1.07 V, WC process, a junction TJ = 110°C, and an artificial smoke test.
Table 6. Estimated Typical I/O Power Dissipation
Interface
Parameter
GVDD (1.8 V)
GVDD (2.5 V) OVDD (3.3 V) Unit
Comments
DDR I/O
65% utilization
2.5 V
Rs = 20 Ω
Rt = 50 Ω
1 pair of clocks
266 MHz, 1
× 32 bits
0.212
0.367
W
Local bus I/O
load = 25 pF
1 pair of clocks
66 MHz, 32 bits
0.12
W
PCI I/O load = 30 pF
66 MHz, 32 bits
0.057
W
QUICC Engine block and
other I/Os
UTOPIA 8-bit 31 PHYs
0.041
W
Mutiply by number
of interfaces used.
TDM serial
0.001
W
TDM nibble
0.004
W
HDLC/TRAN serial
0.003
W
HDLC/TRAN nibble
0.025
W
DUART
0.017
W
MIIs
0.009
W
RMII
0.009
W
Ethernet management
0.002
W
USB
0.001
W
SPI
0.001
W
Timer output
0.002
W
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