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參數(shù)資料
| 型號： | MPC8321EVRADDC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA516 |
| 封裝： | 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, PBGA-516 |
| 文件頁數(shù)： | 75/80頁 |
| 文件大?。?/td> | 1122K |
| 代理商： | MPC8321EVRADDC |
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor
77
Document Revision History
24.6
Configuration Pin Multiplexing
The MPC8323E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 k
Ω on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these
pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize
the disruption of signal quality or speed for output pins thus configured.
24.7
Pull-Up Resistor Requirements
The MPC8323E requires high resistance pull-up resistors (10 k
Ω is recommended) on open drain type pins
including I2C pins, Ethernet Management MDIO pin, and IPIC interrupt pins.
For more information on required pull-up resistors and the connections required for the JTAG interface,
see AN3361, MPC8321E/MPC8323E PowerQUICC Design Checklist, Rev. 1.
25 Document Revision History
Table 66 provides a revision history for this hardware specification.
Table 66. Document Revision History
Rev.
No.
Date
Substantive Change(s)
2
4/2008
Removed Figures 2 and 3 overshoot and undershoot voltage specs from Section 2.1.2, “Power Supply
Voltage Specification,” and footnotes 4 and 5 from Table 1.
Corrected QUIESCE signal to be an output signal in Table 55.
Added column for GVDD (1.8 V) - DDR2 - to Table 6 with 0.212-W typical power dissipation.
Added Figure 3 DDR input timing diagram.
Removed CE_TRB* and CE_PIO* signals from Table 55.
Added three local bus AC specifications to Table 30 (duty cycle, jitter, delay between input clock and
local bus clock).
Added row in Table 2 stating junction temperature range of 0 to 105°C.
Modified Section 2.2, “Power Sequencing,” to include PORESET requirement.
1
6/2007
Correction to descriptive text in Section 2.2.
0
6/2007
Initial release.
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|---|---|
| MPC8321EVRAFDC | 功能描述:微處理器 - MPU 8321 NOPB PBGA W/ ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8321EVRAFDC | 制造商:Freescale Semiconductor 功能描述:Embedded Networking Processor |
| MPC8321EVRAFDCA | 制造商:Freescale Semiconductor 功能描述:POWERQUICC, 32 BIT POWER ARCHITECTURE SOC, 333MHZ E300, QE, - Trays 制造商:Freescale Semiconductor 功能描述:IC MPU PWRQUICC 333MHZ 516BGA 制造商:Freescale Semiconductor 功能描述:MPC8321 Series 32 Bit 333 MHz PowerQUICC II Integrated Communication Processor 制造商:Freescale Semiconductor 功能描述:PowerQUICC, 32 Bit Power Architecture SoC, 333MHz e300, QE, PCI, USB2.0, DDR1/2, |
| MPC8321EZQADDC | 功能描述:微處理器 - MPU 8321 PBGA W/ ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8321EZQAFDC | 功能描述:微處理器 - MPU 8321 PBGA W/ ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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