參數(shù)資料
型號(hào): MPC8321EVRADDC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA516
封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, PBGA-516
文件頁(yè)數(shù): 4/80頁(yè)
文件大?。?/td> 1122K
代理商: MPC8321EVRADDC
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
12
Freescale Semiconductor
DDR1 and DDR2 SDRAM
5.1
Reset Signals DC Electrical Characteristics
Table 11 provides the DC electrical characteristics for the MPC8323E reset signals mentioned in Table 9.
6
DDR1 and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR1 and DDR2 SDRAM interface
of the MPC8323E. Note that DDR1 SDRAM is Dn_GVDD(typ) = 2.5 V and DDR2 SDRAM is
Dn_GVDD(typ) = 1.8 V. The AC electrical specifications are the same for DDR1 and DDR2 SDRAM.
6.1
DDR1 and DDR2 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
MPC8323E when Dn_GVDD(typ) = 1.8 V.
Table 11. Reset Signals DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Output high voltage
VOH
IOH = –6.0 mA
2.4
V
1
Output low voltage
VOL
IOL = 6.0 mA
0.5
V
1
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
1
Input high voltage
VIH
—2.0
OVDD +0.3
V
1
Input low voltage
VIL
–0.3
0.8
V
Input current
IIN
0 V
≤ VIN ≤ OVDD
±5
μA—
Note:
1. This specification applies when operating from 3.3 V supply.
Table 12. DDR2 SDRAM DC Electrical Characteristics for D
n
_GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
D
n
_GV
DD
1.71
1.89
V
1
I/O reference voltage
MVREF
nREF
0.49
× Dn_GVDD
0.51
× Dn_GVDD
V2
I/O termination voltage
VTT
MVREF
nREF – 0.04
MVREF
nREF +0.04
V
3
Input high voltage
VIH
MVREF
nREF + 0.125
D
n
_GVDD +0.3
V
Input low voltage
VIL
–0.3
MVREF
nREF – 0.125
V
Output leakage current
IOZ
–9.9
9.9
μA4
Output high current (VOUT = 1.35 V)
IOH
–13.4
mA
Output low current (VOUT = 0.280 V)
IOL
13.4
mA
Notes:
1. D
n
_GV
DD is expected to be within 50 mV of the DRAM Dn_GVDD at all times.
2. MVREF
nREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF
nREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF
nREF. This rail should track variations in the DC level of MVREFnREF.
4. Output leakage is measured with all outputs disabled, 0 V
V
OUT Dn_GVDD.
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