參數(shù)資料
型號: MPC8308ZQAGD
廠商: Freescale Semiconductor
文件頁數(shù): 43/83頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 473MAPBGA
標準包裝: 84
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 473-LFBGA
供應商設備封裝: 473-MAPBGA(19x19)
包裝: 托盤
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
48
Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
This figure provides the eSDHC clock input timing diagram.
Figure 37. eSDHC Clock Input Timing Diagram
SD Card Output Valid
tODLY
—14
ns
3
SD Card Output Hold
tOH
2.5
ns
3
Notes:
1 The symbols used for timing specifications herein follow the pattern of t
(first three letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH symbolizes eSDHC
full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also
tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O)
going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five
letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2 Measured at capacitive load of 40 pF.
3 For reference only, according to the SD card specifications.
Table 40. eSDHC AC Timing Specifications for High Speed Mode (continued)
At recommended operating conditions NVDD = 3.3 V ± 300 mV.
Parameter
Symbol 1
Min
Max
Unit
Notes
eSDHC
tSHSCKR
External Clock
VM
tSHSCK
tSHSCKF
VM = Midpoint Voltage (NVDD/2)
operational mode
tSHSCKL
tSHSCKH
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