參數(shù)資料
型號(hào): MPC8308ZQAGD
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 22/83頁(yè)
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 473MAPBGA
標(biāo)準(zhǔn)包裝: 84
系列: MPC83xx
處理器類(lèi)型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 473-LFBGA
供應(yīng)商設(shè)備封裝: 473-MAPBGA(19x19)
包裝: 托盤(pán)
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor
29
High-Speed Serial Interfaces (HSSI)
Figure 17. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 18. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 19. Single-Ended Reference Clock Input DC Requirements
10.2.3
Interfacing with Other Differential Signaling Levels
With on-chip termination to XCOREVSS, the differential reference clocks inputs are high-speed current
steering logic (HCSL) compatible and DC coupled.
Many other low voltage differential type outputs like low-voltage differential signaling (LVDS) can be
used but may need to be AC-coupled due to the limited common mode input range allowed (100–400 mV)
for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock
driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to
AC-coupling.
SD_REF_CLK
Vmax < 80 0mV
Vmin > 0V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800mV
SD_REF_CLK
Vcm
200mV < Input Amplitude or Differential Peak < 800mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
SD_REF_CLK
400 mV < SD_REF_CLK Input Amplitude < 800 mV
0V
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