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| 型號： | MPC8308CZQAFD |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 31/83頁 |
| 文件大小： | 0K |
| 描述： | MPU POWERQUICC II PRO 473MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 333MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 473-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 473-MAPBGA（19x19） |
| 包裝： | 托盤 |
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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor
37
PCI Express
11.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 27 is specified using the passive compliance/test measurement load
(Figure 29) in place of any real PCI Express interconnect + RX component. There are two eye diagrams
that must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate
the center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a
transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always
relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
NOTE
It is recommended that the recovered TX UI be calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
AC coupling capacitor
CTX
All Transmitters shall be AC coupled.
The AC coupling is required either within
the media or within the transmitting
component itself. An external capacitor
of 100nF is recommended.
75
—
200
nF
—
Crosslink random timeout
Tcrosslink
This random timeout helps resolve
conflicts in crosslink configuration by
eventually resulting in only one
Downstream and one Upstream Port.
0—1
ms
7
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 29 and measured over any
250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 27.)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total TX
jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The
jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to
the averaged time value.
4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return
loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to
all valid input levels. The reference impedance for return loss measurements is 50
to ground for both the D+ and D– line (that
is, as measured by a vector network analyzer with 50-
probes, see Figure 29). Note that the series capacitors, C
TX, is optional
for the return loss measurement.
5. Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 29 for both VTX-D+ and VTX-D-.
6. See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.
7. See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
Table 34. Differential Transmitter (TX) Output Specifications (continued)
Parameter
Symbol
Comments
Min
Typical
Max
Units Note
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