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參數(shù)資料
| 型號(hào)： | MPC8308CZQAFD |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 23/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC II PRO 473MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 333MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 473-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 473-MAPBGA（19x19） |
| 包裝： | 托盤 |
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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor
3
Electrical Characteristics
2.1.1
Absolute Maximum Ratings
This table lists the absolute maximum ratings.
2.1.2
Power Supply Voltage Specification
This table provides the recommended operating conditions for the device. Note that the values in this table
are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
Table 1. Absolute Maximum Ratings1
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.26
V
—
PLL supply voltage
AVDD1, AVDD2
–0.3 to 1.26
V
—
DDR2 DRAM I/O voltage
GVDD
–0.3 to 1.9
V
—
Local bus, DUART, system control and power management,
eSDHC, I2C, USB, Interrupt, Ethernet management, SPI,
Miscellaneous and JTAG I/O voltage
NVDD
–0.3 to 3.6
V
7
SerDes PHY
XCOREVDD,
XPADVDD,
SDAVDD
–0.3 to 1.26
V
—
eTSEC I/O Voltage
LVDD1, LVDD2
–0.3 to 2.75 or
–0.3 to 3.6
V6, 8
Input voltage
DDR2 DRAM signals
MVIN
–0.3 to (GVDD + 0.3)
V
2, 5
DDR2 DRAM reference
MVREF
–0.3 to (GVDD + 0.3)
V
2, 5
eTSEC
LVIN
–0.3 to (LVDD + 0.3)
V
4, 5,8
Local bus, DUART, system control and power
management, eSDHC, I2C, Interrupt,
Ethernet management, SPI, Miscellaneous
and JTAG I/O voltage
OVIN
–0.3 to (NVDD + 0.3)
V
3, 5,7
Storage temperature range
TSTG
–55 to 150
C—
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed NVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
5. (M, L, O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2
6. The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode.
7. NVDD here refers to NVDDA, NVDDB,NVDDG, NVDDH, NVDDJ, NVDDP_K from the ball map.
8. LVDD1 here refers to NVDDC and LVDD2 refers to NVDDF from the ball map
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