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| 型號： | MPC8240LZU250X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | TBGA-352 |
| 文件頁數(shù)： | 50/52頁 |
| 文件大?。?/td> | 542K |
| 代理商： | MPC8240LZU250X |
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MPC8240 (rev0.5) Hardware Specifications
7
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.1.2 Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8240.
Table 2. Recommended Operating Conditions
Characteristic1
Symbol
Recommended
Value
Unit
Notes
Supply Voltage
Vdd
2.5
± 5%
V
4,6
I/O Buffer supply for PCI and Standard
OVdd
3.3
± 0.3
V
6
Supply Voltages for Memory Bus Drivers
GVdd
3.3
± 5%
V
8
PLL Supply Voltage - CPU Core Logic
AVdd
2.5
± 5%
V
6
PLL Supply Voltage - Peripheral Logic
AVdd2
2.5
± 5%
V
7
DLL Supply Voltage
LAVdd
2.5
± 5%
V
7
PCI Reference
LVdd
5.0
± 5%
V
9,10
3.3
± 0.3
V
9,10
Input Voltage
PCI Inputs
VIN
0 to 3.6 or 5.75
V
2,3
All Other Inputs
0 to 3.6
V
5
Die-Junction Temperature
TJ
0 to 105
°C
Notes:
1
These are the recommended and tested operating conditions. Proper device
operation outside of these conditions is not guaranteed.
2
PCI pins are designed to withstand LVdd + 0.5 V dc when LVdd is connected
to a 5.0V dc power supply.
3
PCI pins are designed to withstand LVdd + 0.5 V dc when LVdd is connected
to a 3.3 V dc power supply.
4
See Section 1.9 “Ordering Information” for details on a modied voltage (Vdd)
version device.
Cautions:
5
Input voltage (VIN) must not be greater than the supply voltage (Vdd/AVdd/
AVdd2/LAVdd) by more than 2.5 V at all times including during power-on
reset.
6
OVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 1.8 V at any
time including during power-on reset.
7
Vdd/AVdd/AVdd2/LAVdd must not exceed OVdd by more than 0.6 V at any
time including during power-on reset.
8
GVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 1.8 V at any
time including during power-on reset.
9
LVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 5.4 V at any
time including during power-on reset.
10 LVdd must not exceed OVdd by more than 3.6 V at any time including during
power-on reset.
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