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參數(shù)資料
| 型號： | MPC8240LZU250X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | TBGA-352 |
| 文件頁數(shù)： | 36/52頁 |
| 文件大?。?/td> | 542K |
| 代理商： | MPC8240LZU250X |
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MPC8240 (rev0.5) Hardware Specifications
41
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
1.7.7 JTAG Conguration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the MPC8240
are available on the internet at www.mot.com/SPS/PowerPC/teksupport/tools/BSDL/) The TRST signal is
optional in the IEEE 1149.1 specication but is provided on all PowerPC implementations. While it is
possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable
power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Since the
JTAG interface is also used for accessing the common on-chip processor (COP) function of PowerPC
processors, simply tying TRST to HRST_CPU/HRST_CTRL is not practical. Note that the two hard reset
signals on the MPC8240 (HRST_CPU and HRST_CTRL) must be asserted and negated together to
guarantee normal operation.
The common on-chip processor (COP) function of PowerPC processors allows a remote computer system
(typically a PC with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG port of the processor,
with some additional status monitoring signals. The COP port requires the ability to independently assert
HRST_CPU/HRST_CTRL or TRST in order to fully control the processor. If the target system has
independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button
switches, then the COP reset signals must be merged into these signals with logic.
The arrangement shown in allows the COP to independently assert HRST_CPU/HRST_CTRL or TRST
while insuring that the target can drive HRST_CPU/HRST_CTRL as well. The COP header shown, adds
many benets including breakpoints, watchpoints, register and memory examination/modication and other
standard debugger features are possible through this interface. Availability of these features can be as
inexpensive as an unpopulated footprint for a header to be added when needed.
1.7.8 PCI Reference Voltage - LVdd
The MPC8240’s PCI reference voltage (LVdd) pins should be connected to 3.3 ± 0.3 V power supply if
interfacing the MPC8240 into a 3.3 V PCI bus system. Similarly, the LVdd pins should be connected to 5.0
± 5% V power supply if interfacing the MPC8240 into a 5 V PCI bus system. For either reference voltage,
the MPC8240 always performs 3.3V signaling as described in the PCI Local Bus Specication (r2.1). The
MPC8240 only tolerates 5V signals when interfaced into a 5 V PCI bus system.
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| MPC8241LVR166D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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| MPC8241LVR266D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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