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參數(shù)資料
| 型號： | MPC8240LZU250X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | TBGA-352 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 542K |
| 代理商： | MPC8240LZU250X |
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36
MPC8240 (rev0.5) Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
PLL Configuration
MPC8240 is in the reset state.The value of the internal pull-up resistor is not guaranteed, but is sufcient
to insure that a '1' is read into conguration bits during reset.
6
Multi-pin signals such as AD[0–31] or DL[0–31] have their physical package pin numbers listed in order
corresponding to the signal names. Ex: AD0 is on pin C22, AD1 is on pin D22,... AD31 is on pin V25.
7
GNT4 is a reset conguration pin and has an internal pull-up resistor which is enabled only when the
MPC8240 is in the reset state.The value of the internal pull-up resistor is not guaranteed, but is sufcient
to insure that a '1' is read into conguration bits during reset.
8
Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this PCI control pin to LVdd.
9VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3 “. DC Electrical Spec-
10 Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this pin to OVdd.
11 Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this pin to GVdd.
12 This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is
sufcient to prevent unused inputs from oating.
13 Output Valid specications for this pin are memory interface mode dependent (Registered or Flow-
through), see Table 10 “. Output AC Timing Specications”.
14 Non-DRAM Access Output Valid specication applies to this pin during non-DRAM accesses, see speci-
cation 12b3 in Table 10 “. Output AC Timing Specications”.
15 This pin is affected by programmable PCI_HOLD_DEL parameter, see Section 1.4.3.3.1 “PCI Signal Out-
16 This pin is an open drain signal.
17 This pin can be programmed to be driven (default) or can be programmed to be open drain; see PMCR2
register description in the MPC8240 User’s Manual for details.
18 This pin is a Sustained Tri-State pin as dened by the PCI Local Bus Specication.
19 These pins are internally connected.
1.6 PLL Conguration
The MPC8240’s internal PLLs are congured by the PLL_CFG[0–4] signals. For a given PCI_SYNC_IN
(PCI bus) frequency, the PLL conguration signals set both the Peripheral Logic/Memory Bus PLL (VCO)
frequency of operation for the PCI-to-Memory frequency multiplying and the 603e CPU PLL (VCO)
frequency of operation for Memory-to-CPU frequency multiplying. The PLL congurations for the
MPC8240 is shown in Table 18.
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