參數(shù)資料
型號： MPC604ERX300XX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, CBGA255
封裝： 21 X 21 MM, 3.30 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255
文件頁數(shù)： 6/29頁
文件大?。?/td> 217K
代理商： MPC604ERX300XX
PRELIMINAR
Y
14
PID9q-604e Hardware Specifications
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Figure 5 provides the JTAG clock input timing diagram.
Figure 5. Clock Input Timing Diagram
Figure 6 provides the TRST timing diagram.
Figure 6. TRST Timing Diagram
8
TCK to output data valid
4
25
ns
3
9
TCK to output high impedance
3
24
ns
3
10
TMS, TDI data setup time
0
ns
11
TMS, TDI data hold time
25
ns
12
TCK to TDO data valid
4
24
ns
13
TCK to TDO high impedance
3
15
ns
Notes:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued)
Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3 ± 5%, GND = 0 V dc, CL = 5 pF, 0 Tj 105 C
Num
Characteristic
Min
Max
Unit
Notes
TCK
2
1
VM
3
VM = Midpoint Voltage (0.9 V)
TRST
TCK
4
5
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