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參數(shù)資料
| 型號： | MPC604ERX300XX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3.30 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 3/29頁 |
| 文件大?。?/td> | 217K |
| 代理商： | MPC604ERX300XX |
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PRELIMINAR
Y
PID9q-604e Hardware Specifications
11
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Figure 3 provides the mode select input timing diagram for the 604e.
Figure 3. Mode Select Input Timing Diagram
1.4.2.3 Output AC Specications
The output specications of the 604e for both driving high and driving low depend on the capacitive loading
on each output and the drive capability enabled for that output. Additionally, the timing specications for
outputs driving low also depend on the voltage swing required to drive to 0.4V. Table 8 provides the output
AC timing specications for a 5pF, 50
W transmission line load. In order to derive the actual timing
specications for a given set of conditions, it is recommended that IBIS simulation models be used. The
IBIS models are currently based on device simulation data. Compatibility mode specications are provided
to support PID9q-604e use in existing designs. Contact the local Motorola or IBM sales ofce for
information on the availability of these models.
Table 8 provides the output AC timing specications for the 604e (refer to Figure 4).
Table 8. Output AC Timing Specifications1
Vdd = AVdd = 1.9
±100 mV dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 Tj 105 C, drive mode [11]6
Num
Characteristic
266, 300, 333 MHz
Unit Notes
Min
Max
Compatibility
Mode
11
SYSCLK to output driven (output enable time)
0.75
0.75 Min
ns
2, 5
12
SYSCLK to TS, XATS, ARTRY, SHD, ABB and
DBB output valid
3.75
4.75 Max
ns
5
13
SYSCLK to all other signals output valid
4.75
5.75 Max
ns
5
14
SYSCLK to output invalid (output hold)
0.0
0.5 Min
ns
2, 5
15
SYSCLK to output high impedance (all signals
except ARTRY, SHD, ABB, DBB, TS, and
XATS)
3.4
4.4 Max
ns
5
16
SYSCLK to output high impedance TS, XATS
3.4
4.4 Max
ns
5
17
SYSCLK to ABB and DBB high impedance
after precharge
1.0* tsysclk
1.0* tsysclk Max
ns
4
18
SYSCLK to ARTRY and SHD high impedance
before precharge
3.4
4.4 Max
ns
5
DRTRY
HRESET
VM
VM = Midpoint Voltage (0.9 V)
10
9
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