
PRELIMINAR
Y
12
PID9q-604e Hardware Specifications
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
19
SYSCLK to ARTRY, and SHD precharge
enable
0.5* tsysclk + 0.75
0.5* tsysclk + 0.75 Max
ns
4
20
Maximum delay to ARTRY and SHD precharge
1.5* tsysclk
1.5* tsysclk Max
ns
4
21
SYSCLK to ARTRY and SHD high impedance
after precharge
2.0* tsysclk
2.0* tsysclk Max
ns
4
Rise time (ARTRY, SHD, ABB, DBB, TS, and
XATS)
1.0
ns
3
Rise time (all signals except ARTRY, SHD,
ABB, DBB, TS, and XATS)
1.0
ns
3
Fall time (ARTRY, SHD, ABB, DBB, TS, and
XATS)
1.0
ns
3
Fall time (all signals except ARTRY, SHD, ABB,
DBB, TS, and XATS)
1.0
ns
3
Notes:
1. All output specications are measured from the 0.9 V level of the rising edge of SYSCLK to the TTL level (0.5
V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 4).
2. All AC timing is based on a 5pF, 50
W transmission line load
3. These specications are nominal values
4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as tsysclk
the numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time
duration (in nanoseconds) of the parameter in question.
5. These specications are nominal values for Fast Out mode; refer to Section 1.8.2, Input and Output Signal
Mode Selection for signal conguration to enable Fast Out mode.The PID9q-604e is tested in Fast Out mode.
Compatibility mode is guaranteed by design and is not tested.
6. To operate in accordance with these specications, the drive mode signals must be congured with
DRVMOD0 = high, and DRVMOD1 = high.
Table 8. Output AC Timing Specifications1 (Continued)
Vdd = AVdd = 1.9
±100 mV dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 Tj 105 C, drive mode [11]6
Num
Characteristic
266, 300, 333 MHz
Unit Notes
Min
Max
Compatibility
Mode