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參數(shù)資料
| 型號： | MPC604ERX300XX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3.30 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 29/29頁 |
| 文件大?。?/td> | 217K |
| 代理商： | MPC604ERX300XX |
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PRELIMINAR
Y
PID9q-604e Hardware Specifications
9
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Figure 1 provides the SYSCLK input timing diagram.
Figure 1. SYSCLK Input Timing Diagram
4
SYSCLK duty cycle
measured at 0.9 V
40
60
40
60
40
60
%
3
SYSCLK jitter
±150
±150
±150
ps
4
604e internal PLL relock
time
100
100
100
ms
3, 5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[03] settings must be chosen such that the
resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not
exceed their respective maximum or minimum operating frequencies. Refer to the
PLL_CFG[03] signal description in Section 1.8, System Design Information, for valid
PLL_CFG[03] settings, and to Section 1.9, Ordering Information, for available frequencies
and part numbers.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 1.8 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design.
5. PLL-relock time is the maximum time required for PLL lock after a stable Vdd, OVdd, AVdd,
and SYSCLK are reached during the power-on reset sequence. Also note that HRESET
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100
ms)
during the power-on reset sequence.
6. 604e processors are tested at the maximum SYSCLK frequencies shown in the AC timing
specications. It is possible to attain higher SYSCLK frequencies through proper system
design.
Table 6. Clock AC Timing Specifications (Continued)
Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0
Tj 105 C
Num
Characteristic
266 MHz
300 MHz
333 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
VM
CVil
CVih
SYSCLK
2
3
4
VM = Midpoint Voltage (0.9 V)
4
1
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