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| 型號： | MN18R1628DF0-CT9 |
| 元件分類： | DRAM |
| 英文描述： | 128M X 18 RAMBUS MODULE, XMA200 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 514K |
| 代理商： | MN18R1628DF0-CT9 |
Page 9
Version 1.2 Dec. 2003
MP18R1624(8)DF0
MN18R1624(8)DF0
AC Electrical Specifications
Adjusted
T
PD Specification
Table 8 : AC Electrical Specifications
Symbol
Parameter and Conditions
Min
Typ
Max
Unit
ZL
Module Impedance of RSL Signals
25.2
28
30.8
ZUL-CMOS
Module Impedance of SCK and CMOS signals
23.8
28
32.2
TPD
Propagation Delay variation of RSL signals. Average clock delay
from pad to pad of all RSL clock nets (CTM, CTMN, CFM and
CFMN)
See
Table10a,b
ns
T
PD
Propagation delay variation of RSL signals with respect to TPD
b,c for 4
and 8 device modules
-21
21
ps
T
PD-CMOS
Propagation delay variation of SCK and CMD signals with respect to an
average clock delay
-250
250
ps
T
PD-
SCK,CMD
Propagation delay variation of CMD signals with respect to SCK signal
-200
200
ps
a. Table 10 lists parameters and specifications for different storage capacity NexMod Modules that use 288Mb RDRAM devices.
b. TPD or Average clock delay is defined as the delay from finger to finger of RSL signal.
c. If the NexMod module meets the following specification, then it is compliant to the specification. If the NexMod module does not meet these specifi-
cations, then the specification can be adjusted by the “Adjusted
T
PD Specification“ table 9 below.
Table 9 : Adjusted
T
PD Specification
Symbol
Parameter and Conditions
Adjusted Min/Max
Absolute
Min / Max
Unit
T
PD
Propagation delay variation of RSL signals with respect to
TPD for 4 and 8 device modules
+/-[17+(18*N*
Z0)]a
-30
30
ps
a. Where:
N = Number of RDRAM devices installed on the NexMod module
Z0 = delta Z0% = (max Z0 - min Z0)/(min Z0)
(max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules)
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