參數(shù)資料
型號(hào)： MN18R1628DF0-CT9
元件分類： DRAM
英文描述： 128M X 18 RAMBUS MODULE, XMA200
文件頁(yè)數(shù)： 13/16頁(yè)
文件大?。?/td> 514K
代理商： MN18R1628DF0-CT9
Page 5
Version 1.2 Dec. 2003
MP18R1624(8)DF0
MN18R1624(8)DF0
SDA
A39
I/O
SVdd
Serial Presence Detect Data(Open Collector I/O)
SIN
A94
I/O
VCMOS
Serial I/O for reading from and writing to the control registers.
Attaches to SIO0 of the first RDRAM device on the module
SVdd
A80
SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1
and SA2
SWP
A59
ISVdd
Serial Presence Detect Write Protection(active high). When
low, the SPD can be written as well as read
PCLK/M
A20
Vdd3.3
Phase detector input(DRCG)
SYN-
CLK/N
A60
Vdd3.3
Phase detector input(DRCG)
REFCLK
A38
Vdd3.3
Reference clock(DRCG)
CTM-
DRCG
A89
IRSL
Clock to master routed to last device in channel. Positive
polarity
CTMN-
DRCG
A88
IRSL
Clock to master routed to last device in channel. Negative
polarity
Vdd3.3
A98, A99
Supply voltage for DRCG
Vcmos
A41, A61, A81, B1, B21, B41
CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT
Vdd
A1, A2, A3, A4, A5, A6, A14, A15,
A16, A21, B61, B78, B79, B81, B82,
B83, B84, B85, B86, B95, B96, B97,
B98, B99
Supply voltage for the RDRAM core and interface logic
Vref
A91, A92, B11, B12
Logic threshold reference voltage for RSL signals.
Signal
Pins
I/O
Type
Description
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