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參數(shù)資料
| 型號(hào)： | ML6510CQ-130 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 150K |
| 代理商： | ML6510CQ-130 |
ML6510
14
REV. 1.0 10/25/2000
Register Definitions
REGISTER
SIZE
FUNCTION
N
7 bit
This register is used to define the ratio for the desired frequency of the primary clock.
R
2 bit
This register defines the frequency of the primary clocks, CLK [0-7].
CM
1 bit
Set CM = 1 when the PECL input reference clock is from another 6510 reference clock output. Set
CM = 0 if the clock reference is TTL or PECL from an external source and minimum phase error
between input and output is desired.
CS
1 bit
CS = 0 selects TTL input clock, CS = 1 selects PECL input clock.
TEST
1 bit
When set to 1, the PLL is bypassed for low frequency testing.
M
6 bit
This register is used to define the ratio for the desired frequency of the primary clock.
DDSK
1 bit
When DDSK is set to 1, deskew is disabled. The chip will provide low skew clocks at the chip output
pins, but trace length variations will not be compensated. When DDSK is set to 0, normal deskew will
provide low skew clocks at the loads. This bit is only for ML6510-130.
ML6510-80 Shift register chain
PCB
trace
impedance
Z0
=
50
Lumped
CL
≤
20pF
FBX
CLKX
ML6510-80
FIRST
-ORDER
MA
TCHED
LO
ADS
ML6510-80
GENERIC
LO
AD
R1
One
way
trip
delay
<
tRANGE/2
PCB
trace
impedance
Z0
=
50
Lumped
CLX
≤
20pF
FBX
CLKX
LO
AD
LO
AD
R1
Length
LX
PCB
trace
impedance
Z0
=
50
Lumped
CLY
≤
20pF
FBY
CLKY
LO
AD
R1
One
way
trip
delay
<
tRANGE/2
Length
LY
|CLX
–
CLY|
<
5pF
|LX
–
LY|
<
4"
ZOX
=
ZOY
ML6510-130 Shift register chain
N1
N2
N3
N4
N5
N6
MSB
R0
LSB
R1
MSB
CS
M0
LSB
TEST
M1
M2
M3
M4
M5
MSB
N0
LSB
SERIAL DATA IN
(from EEPROM,
or
Processor,
or internal ROM)
CM
DDSK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ML6510CQ-80 | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| ML6516241CR | BICMOS SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| ML6516244CT | QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| ML6516444CR | BICMOS SERIES, 16-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| ML65244CS | DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML6510CQ80 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ML6510CQ-80 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩) |
| ML6516244 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6516244CR | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6516244CT | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
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