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參數(shù)資料
| 型號： | ML6510CQ-130 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 150K |
| 代理商： | ML6510CQ-130 |
ML6510
2
REV. 1.0 10/25/2000
BLOCK DIAGRAM
M
N
CLKINL
PLL
PHASE
DETECTOR
CLK0
(to remote chip)
FB0
(from remote chip)
CLK1
FB1
FB7
CLK7
ZERO
DELA
Y
MAX
DELA
Y
DESKEW BUFFER 0
DESKEW BUFFER 1
DESKEW BUFFER 7
MAXIMUM
DELAY
PROGRAMMING
AND
CONTROL
LOGIC
RESET
LOCK
MDIN
R0MMSB
MCLK
MDOUT
MAX
DELA
Y
ZERO
DELA
Y
VOLTAGE
CONTROLLED
DELAY
DRIVE
CIRCUIT
SENSE
CIRCUIT
R
CLKINH
REF
CLOCK
RCLKH RCLKL
FB6
DGND6
CLK6
DVCC67
CLK7
DGND7
FB7
ROMMSB
AVCC2
AGND2
CLKINL
CLK3
DVCC23
CLK2
DGND2
FB2
FB1
DGND1
CLK1
DVCC01
CLK0
DGND0
18
19 20
21
22
DGND3
FB3
AGND1
AVCC1
FB4
DGND4
CLK4
DVCC45
CLK5
DGND5
FB5
FB0
MD
IN
MD
OUT
MCLK
RESET
LOCK
AGND3
AVCC3
RCLKL
RCLKH
CLK
INH
23
28
7
8
9
10
11
12
13
14
15
16
17
65
4
3
2
39
38
37
36
35
34
33
32
31
30
29
140
27
41
26
42
25
43
24
44
ML6510
44-LEAD PLCC (Q44)
TOP VIEW
Pin Connection
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ML6510CQ-80 | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| ML6516241CR | BICMOS SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| ML6516244CT | QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| ML6516444CR | BICMOS SERIES, 16-BIT DRIVER, TRUE OUTPUT, PDSO48 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML6510CQ80 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ML6510CQ-80 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩) |
| ML6516244 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6516244CR | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6516244CT | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
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