參數(shù)資料
型號: ML6510CQ-130
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 15/18頁
文件大?。?/td> 150K
代理商: ML6510CQ-130
ML6510
6
REV. 1.0 10/25/2000
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Programming Timing Characteristics (continued)
tM1
MAIN mode MCLK high time
900
ns
tM2
MAIN mode MCLK low time
900
ns
tM3
MAIN mode MCLK period
1800
ns
tM4
MAIN mode
900
ns
MCLK to MDOUT valid
(EEPROM read time)
Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
Note 2: If ML6510-130 is used in a master-slave mode, the maximum operating frequency is 120MHz.
ML6510 configured with bit CM = 0:
TTL INPUT CLOCK
LOAD [0-7]
1st Order Match
LOAD [0-7] with
no 1st order match
tSKEWF
tSKEWB
tSKEWIO
tSKEWR
PECL INPUT CLOCKS
OR
CLKINH
CLKINL
VICM
AVCC – 0.4V
2.0 V
Note:
All skew is measured at the device load input pin, NOT at the ML6510 clock output pin. Skew is always a positive number, regardless of which edge is leading and
which is trailing.
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