
ML6510
REV. 1.0 10/25/2000
13
Table 2: ML6510-130 ROM Codes
SELECTION BITS
INPUT OUTPUT
CONFIGURATION CODE
FREQ
CODE DESCRIPTION
ROMMSB
MCLK MDOUT (MHz)
(MHz)
CS
CM R1, R0
M
N
DDSK
TEST
0
PECL Input Clock, 1x mode
0
80-130 80-130
1
00
0
1
PECL Input Clock, 0.5x mode
0
1
80-160
40-80
1
01
5
2
0
2
PECL Input Clock, 2x mode
0
1
0
40-65
80-130
1
00
2
5
0
3
PECL Input Clock, 1x mode
0
1
80-130 80-130
1
0
00
0
4
TTL Input Clock, 1x mode
1
0
80-130 80-130
0
00
0
5
TTL Input Clock, 0.5x mode
1
0
1
80-130
40-65
0
01
5
2
0
6
TTL Input Clock, 2x mode
1
0
40-65
80-130
0
00
2
5
0
7
TEST mode, TTL Input clock
1
0-50
0
—
1
Table 1: ML6510-80 rom codes
SELECTION BITS
INPUT
OUTPUT
CONFIGURATION CODE
FREQ
CODE DESCRIPTION
ROMMSB
MCLK MDOUT
(MHz)
CS
CM R1, R0
M
N
TEST
0
PECL Input Clock, 1x mode
0
40-80
1
01
0
1
PECL Input Clock, 0.5x mode
0
1
40-80
20-40
1
10
5
2
0
2
PECL Input Clock, 2x mode
0
1
0
20-40
40-80
1
01
2
5
0
3
PECL Input Clock, 1x mode
0
1
40-80
1
0
01
0
4
TTL Input Clock, 1x mode
1
0
40-80
0
01
0
5
TTL Input Clock, 0.5x mode
1
0
1
40-80
20-40
0
10
5
2
0
6
TTL Input Clock, 2x mode
1
0
20-40
40-80
0
01
2
5
0
7
TEST mode, TTL Input clock
1
0-50
0
—
1
Figure 6. AUX Mode Waveform.
MCLK
(Input to ML6510)
MDOUT
(Input to ML6510)
tA1
tA2
tA5
18
02
01
M5
N0
tA3
tA4
M4