參數(shù)資料
型號: ML60852A
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 52/82頁
文件大?。?/td> 370K
代理商: ML60852A
FEDL60852A-03
1Semiconductor
ML60852A
55/81
EP0 Payload Register (EP0PLD)
Address
0 x 50
Type
6-Bit data
Access type
Read only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
1000
00
After a bus reset
0
1000
00
Definition
0
1
0
Maximum packet size: Since the FIFO of EP0 in the ML60852A has a size of 32 bytes, write 20h into the byte
bMaxPacketSize0 of the device descriptor. The maximum packet size is fixed at 32 bytes
in this EP0PLD register. When a packet with more than 32 bytes is received, the stall bit in
the EP0 status register is asserted and the stall handshake is returned to the host.
EP1, 2 Payload Registers (EP1, 2PLD)
Address
0 x 51, 52
Type
7-Bit data
Access type
Read/Write
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
0
0000
00
Definition
0
Maximum packet size (R/W)
Maximum packet size: Make the local MCU write in this register the value of the descriptor wMaxPacketSize of
the end point selected by the Set_Configuration request from the host. The size of all
packets other than a short packet is specified here in units of a byte.
When the EP has been assigned for reception, if a data packet with a number of bytes
exceeding the maximum packet size specified in this register is received, the receive
packet ready status bit is not asserted, but the stall bit is set in EOP and the stall handshake
is returned to the host.
On the other hand, when the EP has been assigned for transmission, the transmit packet
ready bit is set automatically when writing by the DMA controller of data with the
maximum packet size specified in this register is completed. The content of this register is
ignored during non-DMA transmission of data.
Maximum packet size
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參數(shù)描述
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