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參數(shù)資料
| 型號： | ML60852A |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 37/82頁 |
| 文件大?。?/td> | 370K |
| 代理商： | ML60852A |
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FEDL60852A-03
1Semiconductor
ML60852A
41/81
DMA0, 1 Control Registers (DMA0, 1CON)
Address
0 x 10, 0 x 12
Type
Bit map
Access type
Read/Write
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
The previous value is retained
Definition
Note 1: During the 16-bit mode, the higher order byte of the leading word will be 00h.
Note 2: The higher order byte and the lower order byte are allocated in the little-endian sequence. That is,
the LSB corresponds to AD0 to AD7 and the MSB corresponds to D8 to D15.
During the 16-bit mode and when the packet size is an odd number of bytes, the higher order byte
of the last word will be 00h.
Note 3: When the EP specifications for the DMA channels 0 and 1 both have the same values, DREQ0,
DREQ 1 and DACK0, DACK 1 will respectively be equivalent.
Note 4: The settings of all bits other than bit D7, that is, of bits D0 to D6 should be completed at the time
of initialization (at the latest, before a token packet for EP1 to Ep5 arrives), and should not be
altered thereafter. Write a “1” to D7 in order to temporarily stop DMA transfer in the middle.
When the transfer is restarted by writing a “0” to D7, it is possible to restart the transfer from the
byte (or word) next to the one at which the transfer was interrupted.
DMA Enable
0 = DMA Disabled
1=DMA Enabled
DMA Transfer data width
0 = Byte width (8 bits)
1 = Word width (16 bits) (Note 2)
DMA Transfer mode
0=Single transfer mode
1=Demand transfer mode
DMA Address mode
0 = Single address mode
1 = Dual address mode
DMA Byte count
0 = The number of bytes is not
inserted
1 = The data of the number of
bytes
is
inserted
in
the
leading byte or leading word
of the transfer data. (Note 1)
EP Specification
Specifies the target EP for the DMA transfer
0=EP1, 1=Ep2, 2=EP4, 3=EP5 (Note 3)
DMA Interrupting (Note 4)
0=Normal operation
1=The
DREQ pin is de-asserted
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
| ML61 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Series Positive Voltage Detector |
| ML61_09 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V |
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