參數(shù)資料
型號(hào)： ML60852A
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 29/82頁
文件大?。?/td> 370K
代理商： ML60852A
FEDL60852A-03
1Semiconductor
ML60852A
34/81
EP1 FIFO (EP1FIFO)
Address
0 x 79
Type
Byte data
Access type
Write only
or
Read only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
xxxx
xx
After a bus reset
x
xxxx
xx
Definition
EP1 Transmit data or EP1 receive data
It is possible to specify the direction of transfer of EP1 by setting the EP1 configuration register EP1CONF. The
FIFO address of EP1 is the same in both the transmit direction and the receive direction.
When EP1CONF (D7) = 0, EP1 is in the receive direction and EP1FIFO is in the read-only state.
When EP1CONF (D7) = 1, EP1 is in the transmit direction and EP1FIFO is in the write-only state.
When set for transmission, all bytes of EP1FIFO can be cleared by clearing EP1FIFO (writing a “1” into EP1CONT
(D2)).
EP2 FIFO (EP2FIFO)
Address
0 x 7A
Type
Byte data
Access type
Write only
or
Read only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
xxxx
xx
After a bus reset
x
xxxx
xx
Definition
EP2 Transmit data or EP2 receive data
It is possible to specify the direction of transfer of EP2 by setting the EP2 configuration register EP2CONF. The
FIFO address of EP2 is the same in both the transmit direction and the receive direction.
When EP2CONF (D7) = 0, EP2 is in the receive direction and EP2FIFO is in the read-only state.
When EP2CONF (D7) = 1, EP2 is in the transmit direction and EP2FIFO is in the write-only state.
When set for transmission, all bytes of EP2FIFO can be cleared by clearing EP2FIFO (writing a “1” into EP2CONT
(D2)).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ML60852ATBZ03A 制造商:ROHM Semiconductor 功能描述:
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ML61_09 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V
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