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參數(shù)資料
| 型號： | ML60852A |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 16/82頁 |
| 文件大?。?/td> | 370K |
| 代理商： | ML60852A |
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FEDL60852A-03
1Semiconductor
ML60852A
22/81
(5) Transmit packet ready interrupts (EP1, EP2, EP3, EP4 bulk, EP5 bulk)
These interrupts are generated when it is possible for the local MCU to write the data packet to be sent to the
USB bus from the corresponding EP.
Operation
Source of operation
Description (conditions, responses, etc.)
Transmit packet ready
interrupt generation
ML60852A
(1) In the case of bulk transfer and interrupt transfer
When the respective EP has been set for transmission
(bit D7 of EPnCONF=’1’), the transmit packet ready bit
of the corresponding EP (bit D1 of EPnSTAT) is de-
asserted at which time it is possible to write the transmit
data into the FIFO.
At
this
time,
an
interrupt
is
generated
if
the
corresponding EP transmit packet ready interrupt
enable bit (INTENBL1) has been asserted.
For the second and subsequent packets, in addition to
this condition, before the interrupt is generated, it is
necessary for an ACK response to come from the host
for the packet that has just been sent.
End of transmit packet ready
interrupt
Local MCU (firmware)
(1) In the case of bulk transfer and interrupt transfer
After the one packet of the corresponding EP transmit
data has been written in EPnTXFIFO, write a “1” into the
corresponding transmit packet ready bit (bit D1 of
EPnSTAT). This puts the ML60852A in a state in which
it can transmit the data and the
INTR pin is de-asserted
at the same time.
When the number of bytes in the write data is less than
the maximum packet size, a short packet can be sent by
setting (write ‘1’) the transmit packet ready status of the
endpoint.
Note) EP1,EP2,EP4,and EP5 each has 2 layers of FIFO. Settings in the transmit packet ready control
register (TXPKTCONT) control the assert and de-assert conditions of transmit pactet ready
interrupts. For details, see“Transmit Packet Ready Control Register in INTERNAL REGISTERS.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
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| ML61_09 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V |
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