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參數(shù)資料
| 型號： | MJ80C31U-36:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁數(shù)： | 90/101頁 |
| 文件大小： | 3398K |
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Figure 7-12. Simplified Schematic of AVREG
A simplified schematic of the internal digital voltage regulator is shown in Figure 7-13.
Figure 7-13. Simplified Schematic of DVREG
The block “Low power voltage regulator” within the “Digital voltage regulator” maintains
the DVDD supply voltage when the voltage regulator is disabled, which is the case
during sleep mode. The DVDD voltage drops down to 1.5 V (typical) if the AT86RF212
is in sleep mode; all configuration register values are stored.
The low power voltage regulator is always enabled. Therefore, its bias current
contributes to the leakage current in sleep mode of about 100 nA (typical).
The voltage regulators (AVREG, DVREG) require bypass capacitors for stable
operation. The value of the bypass capacitors determine the settling time of the voltage
regulators. The bypass capacitors shall be placed as close as possible to the pins and
shall be connected to ground with the shortest possible traces (see Table 3-1).
7.5.2 Configuration
The voltage regulators can be configured by the register 0x10 (VREG_CTRL).
It is recommended to use the internal regulators, but it is also possible to supply the low
voltage domains by an external voltage supply. For this configuration, the internal
AT86RF212
8168C-MCU Wireless-02/10
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