參數(shù)資料
型號(hào)： MJ80C31U-36:D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER
文件頁(yè)數(shù)： 54/101頁(yè)
文件大?。?/td> 3398K
79
8168C-MCU Wireless-02/10
AT86RF212
Bit 7 – PA_EXT_EN
Refer to section 9.4.3.
Bit 6 – IRQ_2_EXT_EN
Refer to section 9.5.2.
Bit 5 – TX_AUTO_CRC_ON
The automatic FCS generation is performed with register bit TX_AUTO_CRC_ON = 1,
which is the reset value.
Bit 4 – RX_BL_CTRL
Refer to section 9.6.2.
Bit 3:2 – SPI_CMD_MODE
Refer to section 4.4.1.
Bit 1:0 – IRQ_MASK_MODE, IRQ_POLARITY
Refer to section 4.7.2.
Register 0x06 (PHY_RSSI):
The PHY_RSSI register is a multi-purpose register to indicate FCS validity, to provide
random numbers, and a RSSI value.
Table 6-23. Register 0x06 (PHY_RSSI)
Bit
7
6
5
4
Name
RX_CRC_VALID
RND_VALUE[1]
RND_VALUE[0]
RSSI[4]
Read/Write
R
Reset Value
0
Bit
3
2
1
0
Name
RSSI[3]
RSSI[2]
RSSI[1]
RSSI[0]
Read/Write
R
Reset Value
0
Bit 7 – RX_CRC_VALID
Reading this register bit indicates whether the last received frame has a valid FCS or
not. The register bit is updated at the same time the IRQ_3 (TRX_END) is issued and
remains valid until the next SHR detection. A value of “1” corresponds to a valid FCS; a
value of “0” corresponds to an invalid FCS.
Bit 6:5 – RND_VALUE
Refer to section 9.2.2.
Bit 4:0 – RSSI
Refer to section 6.4.4.
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