參數(shù)資料
型號(hào)： MJ80C31U-36:D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER
文件頁(yè)數(shù)： 36/101頁(yè)
文件大小： 3398K
27
8168C-MCU Wireless-02/10
AT86RF212
Register 0x0F (IRQ_STATUS):
The IRQ_STATUS register contains the status of the pending interrupt requests.
Table 4-17. Register 0x0F (IRQ_STATUS)
Bit
7
6
5
4
Name
BAT_LOW
TRX_UR
AMI
CCA_ED_DONE
Read/Write
R
Reset Value
0
Bit
3
2
1
0
Name
TRX_END
RX_START
PLL_UNLOCK
PLL_LOCK
Read/Write
R
Reset Value
0
By reading the register after an interrupt is signaled at pin 24 (IRQ), the source of the
issued interrupt can be identified. A read access to this register resets all interrupt bits,
and so clears the IRQ_STATUS register.
If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt
event can be read from IRQ_STATUS register, even if the interrupt itself is masked;
refer to Figure 4-18. However, in that case no timing information for this interrupt is
provided. It is recommended to read the interrupt status register 0x0F (IRQ_STATUS)
first to clear the history.
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi purpose register to control various operating
modes and settings of the radio transceiver.
Table 4-18. Register 0x04 (TRX_CTRL_1)
Bit
7
6
5
4
Name
PA_EXT_EN
IRQ_2_EXT_EN
TX_AUTO_CRC_ON
RX_BL_CTRL
Read/Write
R/W
Reset Value
0
1
0
Bit
3
2
1
0
Name
SPI_CMD_MODE
IRQ_MASK_MODE
IRQ_POLARITY
Read/Write
R/W
Reset Value
0
Bit 7 – PA_EXT_EN
RX/TX Indicator, refer to section 9.4.3.
Bit 6 – IRQ_2_EXT_EN
The timing of a received frame can be determined by a separate pin. If register bit
IRQ_2_EXT_EN is set to 1, the reception of a PHR field is directly issued on
pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START). Note that this pin is also active,
even if the corresponding IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK)
is set to 0. The pin remains at high level until the end of the frame receive procedure.
For further details refer to section 9.5.
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