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參數(shù)資料
| 型號(hào)： | MJ80C31U-36:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁數(shù)： | 83/101頁 |
| 文件大?。?/td> | 3398K |
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105
8168C-MCU Wireless-02/10
AT86RF212
7.3.6 Register Description
Register 0x16 (RF_CTRL_0):
This register contains control signals to configure the transmit path.
Table 7-10. Register 0x16 (RF_CTRL_0)
Bit
7
6
5
4
Name
PA_LT[1]
PA_LT[0]
Reserved
Read/Write
R/W
Reset Value
0
1
Bit
3
2
1
0
Name
Reserved
GC_TX_OFFS[1]
GC_TX_OFFS[0]
Read/Write
R
R/W
Reset Value
0
1
Bit 7:6 – PA_LT
These register bits control the lead time of the PA enable signal relative to the TX data
start, see Figure 7-9. This allows to enable the PA 2, 4, 6, or 8 s before the transmit
signal starts. The PA enable signal can also be output at pin DIG3/DIG4 to provide a
control signal for an external RF front-end; for details, refer to section 9.4.
Table 7-11. PA Enable Time Relative to the TX start
Register Bits
Value
PA Enable Lead Time [μs]
0
2
1
4
2
6
PA_LT
3
8
Setting of PA_LT is only effective in TRX_OFF, PLL_ON, and TX_ARET_ON mode.
Bit 5:2 – Reserved
Bit 1:0 – GC_TX_OFFS
These register bits provide an offset between the TX power control word TX_PWR
(register 0x05, PHY_TX_PWR) and the actual TX power. This 2-bit word is added to the
TX power control word before it is applied to the circuit block which adjusts the TX
power. It can be used to compensate differences of the average TX power depending of
the modulation format, see Table 7-16 .
Table 7-12. TX Power Offset
Register Bits
Value
TX Power Offset [dB]
0
-1
1
0
2
+1
GC_TX_OFFS
3
+2
Register 0x05 (PHY_TX_PWR):
This register controls the transmitter output power.
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