參數(shù)資料
型號： MJ80C31U-36:D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER
文件頁數(shù)： 9/101頁
文件大?。?/td> 3398K
38
5.1.4.5 Reset Procedure
The radio transceiver reset procedure is shown in Figure 5-7.
Figure 5-7. Reset Procedure
/RST = L sets all registers to their default values. Exceptions are register bits
CLKM_CTRL (register 0x03, TRX_CTRL_0), refer to section 7.7.4. After releasing the
reset pin (/RST = H), the wake-up sequence including an FTN calibration cycle is
performed, refer to section 7.9. After that, the TRX_OFF state is entered.
Figure 5-7 illustrates the reset procedure once P_ON state was left and the radio
transceiver was not in SLEEP state.
The reset procedure is identical for all originating radio transceiver states except of
states P_ON and SLEEP. Instead, the procedures described in sections 5.1.2.1 and
5.1.2.2 must be followed to enter the TRX_OFF state. If the radio transceiver was in
SLEEP state, the XOSC and DVREG are enabled before entering TRX_OFF state.
Notes
The reset impulse should have a minimum length t10 as specified in section 10.4.
An access to the device should not occur earlier than t11 after releasing the pin /RST;
refer to section 10.4, parameter 10.4.13.
A reset overrides an SPI command that might be queued.
5.1.4.6 State Transition Timing Summary
Transition timings are listed in Table 5-1 and do not include SPI access time if not
otherwise stated. See measurement setup in Figure 3-1.
Table 5-1. State Transition Timing
No.
Symbol
Transition
Time, typ.
Comments
1
tTR1
P_ON
until CLKM
available
330 s
Depends on crystal oscillator setup (Siward A207-011, CL = 10
pF) and external capacitor at DVDD (CB3 = 1 F nom.)
2
tTR2
SLEEP
TRX_OFF
380 s
Depends on crystal oscillator setup (Siward A207-011, CL = 10
pF) and external capacitor at DVDD (CB3 = 1 F nom.);
TRX_OFF state indicated by IRQ_4 (AWAKE_END)
3
tTR3
TRX_OFF
SLEEP
35 cycles
of CLKM
For fCLKM > 250 kHz
4
tTR4
TRX_OFF
PLL_ON
200 s
Depends on external capacitor at AVDD (CB1 = 1 F nom.);
register bit TRX_OFF_AVDD_EN (register 0x0c, TRX_CTRL_2) is
not set; for details, refer to section 7.8.3
AT86RF212
8168C-MCU Wireless-02/10
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