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| 型號(hào)： | MD80C32-20/883:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 20 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 87/395頁(yè) |
| 文件大?。?/td> | 9022K |
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177
ATmega64A [DATASHEET]
8160D–AVR–02/2013
When the Clock Recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection
sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The Clock Recovery logic
then uses samples 8, 9 and 10 for Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with
sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three
samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver
starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is
synchronized and the data recovery can begin. The synchronization process is repeated for each start bit.
21.8.2
Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a
state machine that has 16 states for each bit in Normal mode and eight states for each bit in Double Speed mode.
Figure 21-6 shows the sampling of the data bits and the parity bit. Each of the samples is given a number that is
equal to the state of the recovery unit.
Figure 21-6. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three
samples in the center of the received bit. The center samples are emphasized on the figure by having the sample
number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels,
the received bit is registered to be a logic 1. If two or all three samples have low levels, the received bit is regis-
tered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxD pin.
The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the
receiver only uses the first stop bit of a frame. Figure 21-7 shows the sampling of the stop bit and the earliest pos-
sible beginning of the start bit of the next frame.
Figure 21-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to
have a logic 0 value, the Frame Error n (FEn) flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for
majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 21-7. For
Double Speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The early start bit
detection influences the operational range of the Receiver.
12
34
56
7
8
9
10
11
12
13
14
15
16
1
BIT n
123
4
5
678
1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
12
34
56
7
8
9
10
0/1
STOP 1
123
4
5
6
0/1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
(A)
(B)
(C)
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