
240
ATmega64A [DATASHEET]
8160D–AVR–02/2013
The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are programmed, the
OCDEN Fuse cannot be programmed unless first doing a Chip Erase. This is a security feature that ensures no
back-door exists for reading out the content of a secured device.
The details on programming through the JTAG interface and programming specific JTAG instructions are given in
25.9
On-chip Debug Related Register in I/O Memory
25.9.1
OCDR – On-chip Debug Register
The OCDR Register provides a communication channel from the running program in the microcontroller to the
debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an internal
flag; I/O Debug Register Dirty – IDRD – is set to indicate to the debugger that the register has been written. When
the CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The
debugger clears the IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can only
be accessed if the OCDEN Fuse is programmed, and the debugger enables access to the OCDR Register. In all
other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
25.10 Bibliography
For more information about general Boundary-scan, the following literature can be consulted:
IEEE: IEEE Std 1149.1 - 1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993.
Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison –Wesley, 1992.
Bit
7
654
3210
MSB/IDRD
LSB
OCDR
Read/Write
R/W
Initial Value
0
000
0000