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參數(shù)資料
| 型號： | MCZ33780EG |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 8/37頁 |
| 文件大小： | 0K |
| 描述： | IC MASTER DUAL DBUS DIFF 16-SOIC |
| 標準包裝： | 47 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 808 (CN2011-ZH PDF) |
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Analog Integrated Circuit Device Data
16
Freescale Semiconductor
33780
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The DSIF signal controls the state of the drivers, enabling
the Idle drivers or Signal drivers as is appropriate. A
comparator in the Control block compares the DnL output
voltage with the internal Signal high voltage to determine the
transition from Idle driver to Signal driver. The overvoltage
signal modifies the driver characteristics. This is described in
more detail in the Load Dump Operation section.
The overtemperature signal is also applied to this block.
The Differential Signal Generation block converts the
DSIS signal to the DBUS differential signal voltage levels.
This differential signal is buffered and slew rate controlled by
the Signal drivers. This block is active in all driver modes.
A special requirement of the differential bus is to maintain
a low common mode voltage. This is especially important
during the Idle to Signal transition in order to produce a
smooth changeover to the Signal driver. This is accomplished
by monitoring the common mode voltage and modifying the
Idle driver slew rates. This is the function of the Common
Mode Correction block. An additional feature to make a
smooth changeover and minimize undershoot is to reduce
the slew rate as the changeover point is approached. This
block is not illustrated in Figure 10.
A sense resistor between the Signal driver and the DnH
output detects the Slave device response current. A
comparator (Comp.) generates the signal DSIR that is
supplied to the logic.
The comparator consists of a sense amplifier with offset
(VOS), a filter capacitor and logic gate with buffers to produce
the logic signal (DSIR). The sense amplifier is a ‘gm’ stage
that amplifies the voltage across the sense resistor (RS) to
produce an output current that charges and discharges a filter
capacitor. The voltage across the filter capacitor is compared
with the threshold voltage of the logic gate to produce the
output signal. The voltage across the filter capacitor is
clamped between VCC and ground. See Figure 11.
Figure 11. Receive Filter
Definitions
C = value of filter capacitor = 2.0 pF
VTH = threshold of logic gate = VCC/2 = 2.5 V
A = current gain from sense resistor to filter capacitor =
IO/IBUS = 3.0 A/mA (the amplifier saturates with an
output current of ±40
A)
IBUS[mA] = bus response current.
ITH[mA] = response current threshold = VOS/RS = 6
The filter delay time is given by:
t[
s] = (C * V
TH) / A (IBUS - ITH) = 1.7 / (IBUS- ITH)
The filter characteristic can also be expressed as the
product of the overdrive current (IBUS-ITH) and the duration of
the interference pulse, which must be less than 1.7
s * mA
for the interference to be filtered.
DnH
DSIR
IBUS
RS
VOS
IO
C
gm
VTH
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCZ33780EG | 制造商:Freescale Semiconductor 功能描述:DUAL DBUS MASTER INTERFACE 16SOIC |
| MCZ33780EGR2 | 功能描述:多路器開關(guān) IC DBUS MASTER RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時間（最大值）: 關(guān)閉時間（最大值）: 傳播延遲時間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UQFN-16 |
| MCZ33781EK | 功能描述:輸入/輸出控制器接口集成電路 DBUS2 MASTER STND RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| MCZ33781EKR2 | 功能描述:輸入/輸出控制器接口集成電路 DBUS2 MASTER STND RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| MCZ33784EF | 功能描述:加速計 - 板上安裝 DBUS2 SENSOR INTERFACE RoHS:否 制造商:Murata 傳感軸:Double 加速:12 g 靈敏度: 封裝 / 箱體: 輸出類型:Analog 數(shù)字輸出 - 位數(shù):11 bit 電源電壓-最大:5.25 V 電源電壓-最小:4.75 V 電源電流:4 mA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C |
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