參數(shù)資料
型號: MCZ33780EG
廠商: Freescale Semiconductor
文件頁數(shù): 21/37頁
文件大?。?/td> 0K
描述: IC MASTER DUAL DBUS DIFF 16-SOIC
標準包裝: 47
系列: *
應用: *
接口: *
電源電壓: *
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 16-SOIC W
包裝: 管件
安裝類型: 表面貼裝
產品目錄頁面: 808 (CN2011-ZH PDF)
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
33780
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 24. DBUS Master Registers and Interrupt Block Diagram
DnH REGISTERS
These are read/write registers. There are two of these
registers, one for each of the buses, as shown in Figure 24.
When written to, the data is the high byte of a 9- to16-bit
command. When read, it is the high byte of a 9- to 16-bit
return on the DBUS. Writing to this register does not begin a
DBUS transaction. The low byte must be written to initiate the
DBUS transaction.
The bit assignments are shown in Figure 25. When a short
word of 8 bits is selected for the DBUS (MSn = 1), this register
is skipped in the SPI burst sequence. When the short word
length is set at other than 8 bits, this register will contain the
bits above eight, starting with the ninth bit in the least
significant bit position of the register. Unused bit positions are
don’t care values.
Figure 25. DnH Data Register Bit Assignments
DBUS Encode/Decode Logic
Rx FIFOn
Tx FIFOn
DnH Rx DnL Rx
ERn
DnH Tx
DnL Tx
DnSTAT Register
(Read-Only)
(Write-Only)
ERn
TF
En
TF
N
F
n
RFNEn
DnCTRL Register
TI
En
RIE
n
MS
n
DL
Yn
[B:A]
RFNEn
RIEn
MSn
DLYn[B:A]
TFEn
TIEn
Interrupt Request
DEN Register
ENn
TSn
4 Interrupt Sources
(2 shown)
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset
0
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相關代理商/技術參數(shù)
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MCZ33780EG 制造商:Freescale Semiconductor 功能描述:DUAL DBUS MASTER INTERFACE 16SOIC
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