參數(shù)資料
型號(hào)： MCZ33780EG
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 36/37頁(yè)
文件大?。?/td> 0K
描述： IC MASTER DUAL DBUS DIFF 16-SOIC
標(biāo)準(zhǔn)包裝： 47
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 管件
安裝類型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 808 (CN2011-ZH PDF)
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
33780
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
BUS TRANSMITTER
Idle-to-Signal and Signal-to-Idle Slew Rate (12
≤ V
SUP ≤ 25 V)
tSLEW(IDLE)
2.0
4.5
8.0
V/
s
Signal High-to-Low and Signal Low-to-High Slew Rate (10), (13)
(See Data Valid DSIS to DnD Timing)
tSLEW(SIGNAL)
3.0
4.5
8.0
V/
s
Communication Data Rate Capability (13) (Ensured by Transmitter Data
Valid and Receiver Delay Measurements)
DRATE
–
150
kbps
Signal Bit Time (1 / DRATE)
tBIT
6.67
–
s
INT
Turn ON Delay, DBUS Transaction End to Receive FIFO
INT
tINTON
–
1/3 * tBIT
+0.2
s
INT
Turn ON Delay (C = 100 pF) (12)
CS
to INT Low
tINTON
–
0.2
s
INT
Turn OFF Delay, CS/SCLK Rising Edge to INT High
tINTOFF
–
0.2
s
DBUS Start Delay, CS/SCLK Rising Edge to DBUS (11), (13), (15)
Spread Spectrum Mode Disabled
Spread Spectrum Mode Enabled
tDBUSSTART1
tDBUSSTART2
1/3 * tBIT
–
2/3 * tBIT
4/3 * tBIT
s
Data Valid (10), (12)
DSIF (CS) = 0.5 * VCC to DnD Fall = 5.5 V
DSIS (MOSI) = 0.5 * VCC to DnD Fall = 0.2 * VDnD
DSIS (MOSI) = 0.5 * VCC to DnD Rise = 0.8 * VDnD
DSIF (CS) = 0.5 * VCC to DnD Rise = 6.5 V
tDVLD1
tDVLD2
tDVLD3
tDVLD4
–
0.25
–
6.0
0.8
6.56
1.3
s
Signal Driver Overcurrent Shutdown Delay
tOC
2.0
–
20
s
Signal Low Time for Logic Zero
33.3% Duty Cycle (16)
t0LO
2/3 * tBIT-0.8 2/3 * tBIT-0.6 2/3 * tBIT-0.4
s
Signal Low Time for Logic One
66.7% Duty Cycle (16)
t1LO
1/3 * tBIT-0.8 1/3 * tBIT-0.6 1/3 * tBIT-0.4
s
Notes
10
C = 7.5 nF from DnH to DnL and 4.7 nF from DnH and DnL to GND, capacitor tolerance = ±10%.
11
In the case where the SPI write to DnL (initiating a DBUS transaction start or causing an interrupt) is the last byte in the burst sequence,
timing is from rising edge of CS. Otherwise, timing is from the first SCLK rising edge of the next SPI burst byte.
12
Delays are measured in test mode to determine the delay for analog signal paths.
13
Not measured in production.
14
V
DnD = VDnD(HIGH) - VDnD(LOW).
15
Internal digital delay only.
16
Guaranteed by design.
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V
≤ V
CC ≤ 5.25 V, 9.0 V ≤ VSUP ≤ 25 V, - 40°C ≤ T
A ≤ 85°C unless otherwise
noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCZ33780EG 制造商:Freescale Semiconductor 功能描述:DUAL DBUS MASTER INTERFACE 16SOIC
MCZ33780EGR2 功能描述:多路器開(kāi)關(guān) IC DBUS MASTER RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開(kāi)關(guān)數(shù)量:4 開(kāi)啟電阻（最大值）:7 Ohms 開(kāi)啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 傳播延遲時(shí)間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16
MCZ33781EK 功能描述:輸入/輸出控制器接口集成電路 DBUS2 MASTER STND RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
MCZ33781EKR2 功能描述:輸入/輸出控制器接口集成電路 DBUS2 MASTER STND RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
MCZ33784EF 功能描述:加速計(jì) - 板上安裝 DBUS2 SENSOR INTERFACE RoHS:否 制造商:Murata 傳感軸:Double 加速:12 g 靈敏度: 封裝 / 箱體: 輸出類型:Analog 數(shù)字輸出 - 位數(shù):11 bit 電源電壓-最大:5.25 V 電源電壓-最小:4.75 V 電源電流:4 mA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C
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