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參數(shù)資料
| 型號： | MCP4725A1T-E/CH |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PDSO6 |
| 封裝： | PLASTIC, SOT-23, 6 PIN |
| 文件頁數(shù)： | 34/50頁 |
| 文件大小： | 1494K |
| 代理商： | MCP4725A1T-E/CH |
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MCP4725
DS22039D-page 4
2009 Microchip Technology Inc.
Power Up Time
TPU
—2.5
—
s
VDD = 5V
—5
—
s
VDD = 3V
Exit Power-down Mode,
(Started from falling edge of
ACK pulse)
DC Output Impedance
ROUT
—1
—
Ω
Normal mode (VOUT to VSS)
—1
—
k
Ω
Power-Down Mode 1
(VOUT to VSS)
—100
—
k
Ω
Power-Down Mode 2
(VOUT to VSS)
—500
—
k
Ω
Power-Down Mode 3
(VOUT to VSS)
Supply Voltage Power-up
Ramp Rate for EEPROM
loading
VDD_RAMP
1
—
V/ms
Validation only.
Dynamic Performance
Major Code Transition
Glitch
—
45
—
nV-s
1 LSB change around major
carry (from 800h to 7FFh)
Digital Feedthrough
—
<10
—
nV-s
Digital Interface
Output Low Voltage
VOL
—
0.4
V
IOL = 3 mA
Input High Voltage
(SDA and SCL Pins)
VIH
0.7VDD
——
V
Input Low Voltage
(SDA and SCL Pins)
VIL
—
—0.3VDD
V
Input High Voltage
(A0 Pin)
VA0-Hi
0.8VDD
——
Input Low Voltage
(A0 Pin)
VA0-IL
—
0.2VDD
Input Leakage
ILI
—
±1
A
SCL = SDA = A0 = VSS or
SCL = SDA = A0 = VDD
Pin Capacitance
CPIN
——
3
pF
EEPROM
EEPROM Write Time
TWRITE
—25
50
ms
Data Retention
—
200
—
Years
At +25°C, (Note 2)
Endurance
1
—
Million
Cycles
At +25°C, (Note 2)
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V,
RL = 5 k from VOUT to VSS, CL = 100 pF, TA = -40°C to +125°C. Typical values are at +25°C.
Parameter
Sym
Min
Typ
Max
Units
Conditions
Note 1: Test Code Range: 100 to 4000.
2: This parameter is ensure by design and not 100% tested.
3: Within 1/2 LSB of the final value when code changes from 1/4 to 3/4 (400h to C00h) of full scale range.
4: Logic state of external address selection pin (A0 pin).
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