參數(shù)資料
型號： MCP4725A1T-E/CH
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PDSO6
封裝： PLASTIC, SOT-23, 6 PIN
文件頁數(shù)： 22/50頁
文件大?。?/td> 1494K
代理商： MCP4725A1T-E/CH
2009 Microchip Technology Inc.
DS22039D-page 29
MCP4725
7.5.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must send an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (MCP4725) will leave the data
line HIGH to enable the master to generate the STOP
condition.
FIGURE 7-3:
Data Transfer Sequence On The Serial Bus.
SCL
SDA
(A)
(B)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
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