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參數(shù)資料
| 型號(hào)： | MCP4725A1T-E/CH |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PDSO6 |
| 封裝： | PLASTIC, SOT-23, 6 PIN |
| 文件頁數(shù)： | 17/50頁 |
| 文件大小： | 1494K |
| 代理商： | MCP4725A1T-E/CH |
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MCP4725
DS22039D-page 24
2009 Microchip Technology Inc.
TABLE 6-2:
WRITE COMMAND TYPE
FIGURE 6-1:
Fast Mode Write Command.
C
2
C
1
C0
Command Name
Function
0
X
Fast Mode
This command is used to change the DAC register. EEPROM is not
affected
00
X
“
0
1
0
Write DAC Register
Load configuration bits and data code to the DAC Register
0
1
Write DAC Register
and
EEPROM
(a) Load configuration bits and data code to the DAC Register and
(b) also write the EEPROM
1
0
Reserved
Reserved for future use
1
0
1
Reserved
Reserved for future use
1
0
Reserved
Reserved for future use
1
Reserved
Reserved for future use
Note 1: X = Dont’ Care. Fast Mode does not use C0 bit.
2: The MCP4725 ignores the “Reserved” commands.
1st byte (Device Addressing)
Device Code Address
R/W
ACK (MCP4725)
2nd byte
3rd byte
DAC Register Data (12 bits)
ACK (MCP4725)
Repeat bytes of 2nd and 3rd bytes
Write DAC Register using Fast Mode Write Command: (C2, C1) = (0, 0)
Fast Mode Command (C2, C1 = 0, 0)
ACK (MCP4725)
Power Down Select
START Bit
2nd byte
3rd byte
Read/Write Command
STOP Bit
see Note 1
see Note 2
ACK (MCP4725)
see Note 2
Note 1: A2 and A1 bits are programmed at the factory by hard-wired, and A0 bit is determined by the logic state
of A0 pin.
2: The device updates VOUT at the falling edge of the ACK pulse of the 3rd byte.
11
0
A2
0
A1 A0
0
0 PD1 PD0 D11
D8
D10 D9
D7 D6 D5 D4 D3
D0
D2 D1
0
PD1 PD0 D11
D8
D10 D9
D7 D6 D5 D4 D3
D0
D2 D1
Bits
ACK (MCP4725)
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