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參數(shù)資料
| 型號： | MCIMX535DVV1B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
| 封裝： | 19 X 19 MM, 0.80, MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529 |
| 文件頁數(shù)： | 35/204頁 |
| 文件大?。?/td> | 5605K |
| 代理商： | MCIMX535DVV1B |
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Modules List
i.MX53xD Applications Processors for Consumer Products, Rev. 3
Freescale Semiconductor
13
RTIC
Run-Time
Integrity Checker
Security
Protecting read only data from modification is one of the basic elements in
trusted platforms. The run-time integrity checker, version 3 (RTIC) block is
a data-monitoring device responsible for ensuring that the memory content
is not corrupted during program execution. The RTIC mechanism
periodically checks the integrity of code or data sections during normal OS
run-time execution without interfering with normal operation. The purpose
of the RTIC is to ensure the integrity of the peripheral memory contents,
protect against unauthorized external memory elements replacement and
assist with boot authentication.
SAHARA
Security
Accelerator
Security
SAHARA (symmetric/asymmetric hashing and random accelerator),
version 4, is a security coprocessor. It implements symmetric encryption
algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA
and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and
a hardware true random number generator. It has a slave IP Bus interface
for the host to write configuration and command information, and to read
status information. It also has a DMA controller, with an AHB bus interface,
to reduce the burden on the host to move the required data to and from
memory.
SATA
Serial ATA
Connectivity
Peripherals
SATA HDD interface, includes the SATA controller and the PHY. It is a
complete mixed-signal IP solution for SATA HDD connectivity.
SCCv2
Security
Controller, ver. 2
Security
The security controller is a security assurance hardware module designed
to safely hold sensitive data, such as encryption keys, digital right
management (DRM) keys, passwords and biometrics reference data. The
SCCv2 monitors the system’s alert signal to determine if the data paths to
and from it are secure, that is, it cannot be accessed from outside of the
defined security perimeter. If not, it erases all sensitive data on its internal
RAM. The SCCv2 also features a key encryption module (KEM) that allows
non-volatile (external memory) storage of any sensitive data that is
temporarily not in use. The KEM utilizes a device-specific hidden secret key
and a symmetric cryptographic algorithm to transform the sensitive data
into encrypted data.
SDMA
Smart Direct
Memory Access
System
Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It helps in maximizing
system performance by off loading various cores in dynamic data routing.
The SDMA features list is as follows:
Powered by a 16-bit instruction-set micro-RISC engine
Multi-channel DMA supports up to 32 time-division multiplexed DMA
channels
48 events with total flexibility to trigger any combination of channels
Memory accesses including linear, FIFO, and 2D addressing
Shared peripherals between ARM and SDMA
Very fast context-switching with two-level priority-based preemptive
multi-tasking
DMA units with auto-flush and prefetch capability
Flexible address management for DMA transfers (increment, decrement,
and no address changes on source and destination address)
DMA ports can handle unidirectional and bidirectional flows (copy mode)
Up to 8-word buffer for configurable burst transfers to / from the EXTMC
Support of byte swapping and CRC calculations
A library of scripts and API is available
Table 2. i.MX53xD Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCL908QY1DWE | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO16 |
| MCL908QY1CDWE | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO16 |
| MCL908QT4CPE | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDIP8 |
| MCL908QY2CDTE | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO16 |
| MCL908QY1CDT | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX535DVV1C | 功能描述:處理器 - 專門應(yīng)用 IMX53 REV 2.1 COMM RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX535DVV1C | 制造商:Freescale Semiconductor 功能描述:IMX53 REV 2.1 COMM |
| MCIMX535DVV1C2 | 制造商:Freescale Semiconductor 功能描述:MCIMX535DVV1C2 - Bulk |
| MCIMX535DVV1CR2 | 功能描述:處理器 - 專門應(yīng)用 iMX53 Rev 2.1 Comm RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX535DVV2C | 功能描述:處理器 - 專門應(yīng)用 iMX53 Rev 2.1 Comm RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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