參數(shù)資料
型號: MCIMX31VMN5CR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 532 MHz, MICROPROCESSOR, PBGA473
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-473
文件頁數(shù): 61/122頁
文件大?。?/td> 1418K
代理商: MCIMX31VMN5CR2
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Freescale Semiconductor
43
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Test conditions: load capacitance, 25 pF. Recommended drive strength for all
controls, address, and BCLK is Max drive.
basic WEIM accesses to external memory devices with the timing parameters mentioned in
Table 33 for specific control parameter settings.
WE8
Clock rise/fall to OE Invalid
–3
3
ns
WE9
Clock rise/fall to EB[x] Valid
–3
3
ns
WE10
Clock rise/fall to EB[x] Invalid
–3
3
ns
WE11
Clock rise/fall to LBA Valid
–3
3
ns
WE12
Clock rise/fall to LBA Invalid
–3
3
ns
WE13
Clock rise/fall to Output Data Valid
–2.5
4
ns
WE14
Clock rise to Output Data Invalid
–2.5
4
ns
WE15
Input Data Valid to Clock rise, FCE=0
FCE=1
8
2.5
ns
WE16
Clock rise to Input Data Invalid, FCE=0
FCE=1
–2
ns
WE17
ECB setup time, FCE=0
FCE=1
6.5
3.5
ns
WE18
ECB hold time, FCE=0
FCE=1
–2
2
ns
WE19
DTACK setup time1
0—
ns
WE20
DTACK hold time1
4.5
ns
WE21
BCLK High Level Width2, 3
T/2–3
ns
WE22
BCLK Low Level Width2, 3
T/2–3
ns
WE23
BCLK Cycle time2
15
ns
1 Applies to rising edge timing
2 BCLK parameters are being measured from the 50% VDD.
3 The actual cycle time is derived from the AHB bus clock frequency.
Table 33. WEIM Bus Timing Parameters (continued)
ID
Parameter
Min
Max
Unit
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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