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參數(shù)資料
| 型號： | MCIMX31VMN5CR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 532 MHz, MICROPROCESSOR, PBGA473 |
| 封裝： | 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-473 |
| 文件頁數(shù)： | 119/122頁 |
| 文件大?。?/td> | 1418K |
| 代理商： | MCIMX31VMN5CR2 |
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MCIMX31/MCIMX31L Technical Data, Rev. 4.1
96
Freescale Semiconductor
Electrical Characteristics
4.3.22
SSI Electrical Specifications
This section describes the electrical information of SSI. Note the following pertaining to timing
information:
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX signals when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
4.3.22.1
SSI Transmitter Timing with Internal Clock
Figure 81 depicts the SSI transmitter timing with internal clock, and Table 60 lists the timing parameters.
SJ11
TCK low to TDO high impedance
—
44
ns
SJ12
TRST assert time
100
—
ns
SJ13
TRST set-up time to TCK low
40
—
ns
1 On cases where SDMA TAP is put in the chain, the max TCK frequency is limited by max ratio of 1:8 of SDMA core frequency
to TCK limitation. This implies max frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
2 V
M - mid point voltage
Table 59. SJC Timing Parameters (continued)
ID
Parameter
All Frequencies
Unit
Min
Max
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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