參數(shù)資料
型號(hào): MCIMX27
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processor(多媒體應(yīng)用處理器)
中文描述: 多媒體應(yīng)用處理器(多媒體應(yīng)用處理器)
文件頁數(shù): 84/118頁
文件大?。?/td> 1159K
代理商: MCIMX27
i.MX27 Data Sheet, Advance Information, Rev. 0.1
84
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
3.5.17.2
SSI Receiver Timing with Internal Clock
Figure 46
and
Figure 47
show the SSI receiver timing with internal clock, and
Table 46
lists the timing
parameters.
Figure 46. SSI Receiver with Internal Clock Timing Diagram
Synchronous Internal Clock Operation
SS42
SRXD setup before (Tx) CK falling
10.0
ns
SS43
SRXD hold after (Tx) CK falling
0
ns
SS52
Loading
25
pF
Table 45. SSI Transmitter with Internal Clock Timing Parameters (continued)
ID
Parameter
Min
Max
Unit
SS50
SS48
AD1_TXC
(Output)
AD1_TXFS (bl)
(Output)
AD1_TXFS (wl)
(Output)
AD1_RXD
(Input)
AD1_RXC
(Output)
SS1
SS4
SS2
SS51
SS20
SS21
SS49
SS7
SS9
SS11
SS13
SS47
SS3
SS5
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